High Performance Reconfigurable Computing: Research and Education
Abstract
Radar processing, remote sensing, object detection, autonomous vehicle path planning, and predictive simulation constitute a class of army applications. Those future army applications use high definition images, videos and context information to provide assistance to soldiers by providing lethality protections. Those floating point algorithms are difficult to accelerate on general purpose processors or graphic processors with limited power consumption. When hardware designers accelerate the algorithm using customized floating-point hardware units on FPGAs, it may be time consuming to explore the design space due to various parameters such as resource utilization, accuracy, power consumption, and performance values. It is critical to explore this design space early to ensure that the algorithm can be efficiently mapped onto an FPGA. Our research presents a reconfigurable acceleration environment while addressing the problem of porting High Performance Computing (HPC) applications directly to Field Programmable Gate Array (FPGA)-based architectures. Our methodology presents the development of a comprehensive floating point library of essential functions for scientific applications; demonstrating the order of magnitude speedup of reconfigurable computing applications and the effectiveness of a design framework for both development and test of scientific algorithms. Finally, we demonstrate accessing these FPGA-based solutions from a remote site.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 09, 2016
- Accession Number
- AD1063216
Entities
People
- Clay Gloster