Agile 3D Memory Interfaces

Abstract

The DiRAM4 memory permits fast random access of DRAM via 64 bidirectional memory ports. A memory controller was designed and verified that is suited for interfacing a multicore CPU to this unique DRAM.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 2019
Accession Number
AD1066447

Entities

People

  • Lee Baker
  • Paul D Franzon
  • Theodoros Nigussie

Organizations

  • North Carolina State University

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Air Force
  • Air Force Research Laboratories
  • Central Processing Units
  • Clocks
  • Content Addressable Memory
  • Data Rate
  • Decoders
  • Environment
  • Generators
  • Government Procurement
  • Governments
  • Information Exchange
  • Instructions
  • North Carolina
  • Specifications
  • Technology Transfer
  • Verification

Fields of Study

  • Psychology

Readers

  • Parallel and Distributed Computing.
  • Robotics and Automation.