Robust Logic Obfuscation for Trusted Design Synthesis
Abstract
Logic obfuscation/encryption/locking refers to a class of techniques to prevent IC counterfeiting, reverse engineering, piracy, unauthorized over production or use. In these methods, a logic design is encrypted during or after logic synthesis and a key is generated. The encrypted logic design may be fabricated at a foundry which is untrusted. The key generated at the time of encryption is provided to a trusted user and should be supplied during operation. Valid outputs are produced by the IC if and only if a valid key is supplied. In the past few years, several proposed logic obfuscation methods were shown to be vulnerable to a variety of attacks including the satisfiability attack, skew attack, logic removal attack etc. Further, it is hard to integrate some of the proposed obfuscation methods with standard synthesis tools and methodologies. In this paper, we report our efforts to develop robust obfuscation methods compatible with COTS logic synthesis tools. We explore the use of sub-circuit obfuscation using look-up tables and logic duplication to improve the quality of encryption. Experimental results show negligible area overhead and robust encryption for several benchmark circuits. In addition, we discuss how these methods can be integrated with a COTS logic synthesis tools.1
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 25, 2019
- Accession Number
- AD1075412
Entities
People
- Ranga Vemuri
- Sanjana Sekar
Organizations
- University of Cincinnati