Interoperability and Cold-Spare Support for VLSI ICs Using a System-in-Package I/O Kit

Abstract

VLSI ICs using sub-100 nm CMOS technology provide high speed and low power relative to larger geometry technology. However, at voltages above the breakdown voltage of individual 1/0 transistors, cold-spare support and interoperability with heritage I/O standards are problematic. A System-in-Package (SiP) methodology leveraging BAE Systems' family of radiation-hardened by design (RHBD) I/O chiplets simplifies VLSI IC design while supporting 3.3 V I/O and cold-spare operation. The SiP methodology and chiplets described support multiple technology nodes from 90 nm to at least 7 nm. Tristate I/O, Flash memory interface and ANSI/Vita 78 Space VPX applications illustrate use of the I/O chiplets.

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Document Details

Document Type
Technical Report
Publication Date
Mar 25, 2019
Accession Number
AD1076206

Entities

People

  • Alan Dennis
  • Dale A. Rickard
  • Daniel Stanley
  • Jason F. Ross
  • John T. Matta
  • Joseph R. Marshall
  • Keith Sturcken
  • Lori D. Dennis
  • Richard J. Ferguson

Tags

Communities of Interest

  • Advanced Electronics
  • Air Platforms
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Circuits
  • Energy Consumption
  • High Reliability
  • High Voltage
  • Integrated Circuits
  • Low Voltage
  • Memory Devices
  • Power Converters
  • Radiation
  • Radiation Effects
  • Reliability
  • Semiconductors
  • Space Systems
  • Standards
  • Transceivers
  • Utility Aircraft
  • Very Large Scale Integration

Readers

  • Integrated Circuit Design and Technology.

Technology Areas

  • Space
  • Space - Hall-Effect Thruster