Reverse Engineering RISC-V Generator-Based Designs for Trust and Assurance
Abstract
We reverse engineered the open source Rocket-Chip system-on-a-chip (SoC) generator so we could understand the constructs and IP generation in sufficient detail to trust it for technology transition into our own SoC. We investigated its parameterization and use, configuration of the core, design of generated interfaces and peripherals, and how it ultimately generates Verilog register transfer language code that will be input to the synthesis work flow. Our goal was to understand and verify the assumptions involved in generation at each stage of the tool chain so we can have higher assurance in our ultimate design, and that we could verify the IP we will be using in our system. We discuss the reverse engineering methodology we used to gain precise information about details of the chip, and discuss areas for future work in creating tests and extracting information to verify generator-based designs.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 01, 2019
- Accession Number
- AD1077486
Entities
People
- Adam Bryant
- Jeffrey Durrum
- Jeremy Porter