Digital Logic Gate Characterization with Gallium Nitride Transistor

Abstract

This thesis presents work on the development of digital logic gates using Gallium Nitride (GaN) transistors in a 0.25 m process. The allowed minimum width of 12 m is reduced to 5 m in order to observe scalability and to measure the performance benets of smaller device sizes in the GaN process. Due to poor modeling, the designed Buffered FET Logic INV, NOR2, and NAND2 are designed for functionality over performance, resulting from the risk of failure without proper simulations. A preliminary test plan was developed and executed to prove the functionality of the devices across varying temperatures, voltages, and input frequencies, with initial tests indicating that the devices are fully functional across these parameters.

Document Details

• Document Type: Technical Report
• Publication Date: Aug 01, 2019
• Accession Number: AD1079428

Entities

People

• Timothy Heaton

Organizations

• Ohio State University

Tags

Communities of Interest

• Advanced Electronics

DTIC Thesaurus Topics

• Air Force
• Air Force Facilities
• Band Gaps
• Circuits
• Compound Semiconductors
• Crystal Lattices
• Diodes
• Electrical Engineering
• Electron Mobility
• Electronics
• Electronics Laboratories
• Energy Bands
• Field Effect Transistors
• Frequency
• Gallium
• Gallium Nitrides
• High Electron Mobility Transistors
• Integrated Circuits
• Logic
• Logic Gates
• Materials
• Modules (Electronics)
• Nand Gates
• Nitrides
• Power Electronics
• Power Supplies
• Semiconductor Devices
• Semiconductors
• Simulations
• Transistors

Readers

• Integrated Circuit Design and Technology.
• Semiconductor Device Technology
• Systems Analysis and Design

Technology Areas

• Microelectronics
• Microelectronics - Microelectromechanical Systems