Design of a Memristive Dynamic Adaptive Neural Network Array (MRDANNA)

Abstract

The objective of this effort was to build affordable, manufacturable, low power, dynamic neuromorphic computing platform for handling spiky, highly variable information/data, as well as develop a low-power, hybrid memristor/CMOS neuron / synapse implementation for implementation of a hardware-based dynamic neural network array. The approach was to leverage hybrid CMOS/memristor encryption project to design, fabricate, and test memristor/CMOS neurons / synapses, and integrate them with existing FPGA implementations for full-scale dynamic neural network array demonstration. In addition, to make a module design kit library available for other circuits and architectures, thus making advancements in this effort useful to future designs that utilize hybrid CMOS/memristor technologies.

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Document Details

Document Type
Technical Report
Publication Date
Aug 28, 2019
Accession Number
AD1079475

Entities

People

  • Garrett S. Rose
  • James S. Plank
  • Mark Dean

Organizations

  • University of Tennessee

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Air Force
  • Air Force Research Laboratories
  • Application Software
  • Artificial Intelligence Software
  • Autonomous Navigation
  • Complementary Metal-Oxide Semiconductors
  • Computer Programming
  • Computers
  • Energy Consumption
  • Field Programmable Gate Arrays
  • Integrated Circuits
  • Machine Learning
  • Memristors
  • Neural Networks
  • Robot Navigation
  • Very Large Scale Integration
  • Waveforms

Readers

  • Integrated Circuit Design and Technology.
  • Neural Network Machine Learning.

Technology Areas

  • AI & ML
  • AI & ML - Neural Networks