Flexible Specification, Analysis, and Implementation of Self-Timed Circuits
Abstract
The key result from this effort was the development of a methodology for the hierarchical, formal verification of self-timed circuit models. This has been a goal of the self-timed research community for many years, and this result was documented in the form of two International Symposium on Asynchronous Circuits and Systems (ASYNC) publications and a PhD dissertation where the methodology was described in detail. In addition, the formalization of self-timed circuit models is captured in a set of ACL2 models.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 2019
- Accession Number
- AD1080681
Entities
People
- Warren A. Jr Hunt
Organizations
- University of Texas at Austin