Triple Modular Redundancy MIPS Architecture Version 1.4

Abstract

This report describes in detail the architecture of a Triple Modular Redundancy (TMR) MIPS processor based upon the Basic MIPS processor. The TMR MIPS processor is used for Adaptive-Hybrid Redundancy research. There may be many other applications for the TMR MIPS processor beyond this specific research area.

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Document Details

Document Type
Technical Report
Publication Date
Sep 12, 2019
Accession Number
AD1083723

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  • Nicolas S. Hamilton

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  • Air Force Institute of Technology

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