Implementing the NASA Deep Space LDPC Codes for Defense Applications

Abstract

Selected codes from, and extended from, the NASA's deep space low-density parity-check (LDPC) codes are implemented for high speed defense applications. This is part of an effort to build Government reference waveform implementations to assist defense acquisition programs and to promote waveform reuse. Details of the decoder implementation, including memory layout, parallelization architecture, layered-decoding scheduling, and field programmable gate array (FPGA) resource utilization are presented.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 2013
Accession Number
AD1107291

Entities

People

  • Jeffrey P. Long
  • Wiley H. Zhao

Organizations

  • MITRE Corporation

Tags

Communities of Interest

  • Advanced Electronics
  • Space

DTIC Thesaurus Topics

  • Acquisition
  • Algorithms
  • Communication Systems
  • Computing System Architectures
  • Data Rate
  • Data Transmission
  • Decoders
  • Decoding
  • Deep Space
  • Electronic Mail
  • Field Programmable Gate Arrays
  • Global Positioning Systems
  • Iterations
  • Low Density
  • Military Acquisition
  • Network Protocols
  • Parallel Computing
  • Parallel Processing
  • Processing Equipment
  • Radio Frequency
  • Rotation
  • Scheduling (Production)

Fields of Study

  • Physics

Readers

  • Defense Acquisition Program Management
  • Parallel and Distributed Computing.
  • Radio communications and signal processing.

Technology Areas

  • Space