Parallel Extensions to Single-Path Delay-Feedback FFT Architectures

Abstract

Pipelined Fast Fourier Transform (FFT) architectures, which are efficient for long instances (32k points and greater), are critical for modern digital communication and radar systems. For long instances, Single-Path Delay-Feedback (SDF) FFT architectures minimize required memory, which can dominate circuit area and power dissipation. This paper presents a parallel Radix-22 SDF architecture capable of significantly increased pipelined throughput at no cost to required memory or operating frequency. A corresponding parallel coefficient generator is also presented. Resource utilization results and analysis are presented targeted for a 45nm silicon-on-insulator (SOI) application-specific integrated circuit (ASIC) process.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Jan 01, 2010
Accession Number
AD1107303

Entities

People

  • Albert A. Conti
  • Brett W. Dickson

Organizations

  • MITRE Corporation

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Application-Specific Integrated Circuits
  • Applied Mathematics
  • Circuits
  • Communication Systems
  • Computational Biology
  • Computers
  • Delay Lines
  • Digital Communications
  • Digital Signal Processing
  • Electrical Engineering
  • Electronics
  • Energy Efficiency
  • Engineering
  • Engineers
  • Fast Fourier Transforms
  • Frequency
  • Lepidoptera
  • Parallel Computing
  • Parallel Processing
  • Radar
  • Signal Processing

Fields of Study

  • Engineering

Readers

  • Graph Algorithms and Convex Optimization.
  • Integrated Circuit Design and Technology.
  • Radio communications and signal processing.

Technology Areas

  • Microelectronics