MITRE Common Interface for Register Transfer Level Models Using Open Core Protocol Profiles

Abstract

This document describes a set of standard interfaces for register transfer level (RTL) blocks developed at MITRE. The interfaces leverage the industry standard Open Core Protocol (OCP) to define the connections between blocks. The interfaces are only intended to describe the connections between blocks, not connections external to a device (e.g. field programmable gate array (FPGA) or application specific integrated circuit (ASIC). The initial focus of these interfaces is on blocks which generate, manipulate or route data samples through the platform. The exact definition of a block is purposely left vague since it will vary with the application. Having a common interface structure simplifies reuse and compatibility of blocks between projects.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 2009
Accession Number
AD1108525

Entities

People

  • Karl T. Wagner

Organizations

  • MITRE Corporation

Tags

Communities of Interest

  • Advanced Electronics
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Abstracts
  • Algorithms
  • Application-Specific Integrated Circuits
  • Cecum
  • Circuits
  • Coding
  • Converters
  • Corporations
  • Data Processing
  • Diagrams
  • Field Programmable Gate Arrays
  • Flow
  • Frequency
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  • Infrastructure
  • Integrated Circuits
  • Intermediate Frequencies
  • Phase Diagrams
  • Radio Frequency
  • Specifications
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Fields of Study

  • Computer science

Readers

  • Database Systems and Applications
  • Integrated Circuit Design and Technology.
  • Systems Analysis and Design