IARPA Digital Superconducting Circuit Fabrication (C3)
Abstract
Todays state-of-the-art computer systems are a result of steady predictable scaling of silicon CMOS (complementary metal-oxide semiconductor) integrated circuit technology, as shrinking transistor dimensions over the past several decades have enabled a more than 10,000x increase in the number of transistors on a single processor chip. However, the energy dissipation of CMOS transistors is reaching physical limits, and has become a difficult barrier to building more powerful supercomputers. Advances in "beyond CMOS" device technologies are now seen as a key step towards achieving the next major leap in high-performance computing. Under the IARPA-funded Cryogenic Computing Complexity (C3) program MIT Lincoln Laboratory (MIT-LL) developed state-of-the-art integrated circuit fabrication capability for the development and demonstration of SFQ-based integrated circuits for high-performance computing. With this microfabrication process capability, MIT-LL performed research foundry fabrication of circuits designed by C3 design team performers. In addition, MIT-LL developed, and provided as a research foundry capability for a superconducting multi-chip module (S-MCM) process comprised of passive superconducting wiring layers on a silicon substrate. Using flip-chip attachment, this process provides lossless interconnection between individual SFQ chips.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 16, 2020
- Accession Number
- AD1109536
Entities
People
- Leonard Johnson
Organizations
- MIT Lincoln Laboratory