Optimization and Exploration of Trusted Low-Power High Performance Computer Architectures
Abstract
The research objectives of this project are to design, develop, and evaluate multi-core hardware support for secure computer architectures at then at the nanometer level. Many of these architectures are currently or will be employed in advanced architectures that may have secure capabilities within the Air Force Research Laboratory in Rome, NY. This will be accomplished by designing complete design flow integration with commercial and open-source Electronic Design Automation (EDA) tools. The design flow will take a high-level system-level architecture description as inputs along with area, critical path delay, and power dissipation constraints. Based on the System-on-Chip (SoC) architecture description and design constraints, the tools will automatically generate synthesizable hardware description language (HDL) models, embedded memories, and custom components to implement the specified very large scale integration (VLSI) architecture.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 2021
- Accession Number
- AD1136183
Entities
People
- James Stine
Organizations
- Oklahoma State University–Stillwater