Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizable PLL
Abstract
This letter presents a 16-nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4 GHz at 0.98 V, yielding a peak throughput of 695 Giga RISC-V instructions/s (GRVIS), a peak energy efficiency of 314.89 GRVIS/W, and a record 825 320 CoreMark benchmark score. Unlike previously reported [1], this new score was obtained without modifying the core benchmark code. The main feature is the NoC architecture, which uses only 1881 micrometers 2 per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 18, 2019
- Accession Number
- AD1143294
Entities
People
- Anuj Rao
- Aporva Amarnath
- Austin Rovinski
- Bandhav Veluri
- Christopher Batten
- Christopher Torng
- Chun Zhao
- Dustin Richmond
- Julian Puscar
- Khalid Al-hawaj
- Luis Vega
- Michael Taylor
- Paul Gao
- Ritchie Zhao
- Ronald G. Dreslinski
- Scott Davidson
- Shaolin Xie
- Steve Dai
- Tutu Ajayi
- Zhiru Zhang
Organizations
- University of California, San Diego