Scale Control Processor Test-Chip
Abstract
We are investigating vector-thread architectures which provide competitive performance and efficiency across a broad class of application domains [1, 4]. Vector-thread architectures unify data-level, thread-level, and instruction-level parallelism, providing new ways of parallelizing codes that are difficult to vectorize or that incur excessive synchronization costs when multithreaded. To illustrate these ideas we have developed the Scale processor, which is an example of a vector-thread architecture designed for low-power and high-performance embedded systems. The prototype includes a single-issue 32-bit RISC control processor, a vector-thread unit which supports up to 128 virtual processor threads and can execute up to 16 instructions per cycle, and a 32 KB shared primary cache.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 11, 2007
- Accession Number
- AD1143527
Entities
People
- Christopher Batten
- Krste Asanovic
- Ronny Krashinsky
Organizations
- Massachusetts Institute of Technology