Spiders for FPGA Applications
Abstract
This is a report on the abstract structure of spiders for applications. A spider is a realtime monitor of Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). The FPGAs and CPLDs are assumed to contain applications coded in VHDL. Each spider is associated with specific logic statements expressing conditions in the application code being monitored. Each spider also contains mechanisms for mitigating the effects of an exploit, either malicious, due to an error in design, or due to a hardware fault. Spiders can be written in any language provided there is a translator into a language that vendor supplied tools support. Eventually, spiders will be automatically compiled from logic statements and mitigation code to produce either VHDL code or ReWire code. ReWire has its own compiler that produces either VHDL or Verilog code, which would then subsequently be included in the application.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 07, 2022
- Accession Number
- AD1171226
Entities
People
- Christopher Belmonte
- Gerard Allwein
Organizations
- United States Naval Research Laboratory