Spider for a Traffic Light
Abstract
This is a report on a spider for a traffic light application. A spider is a realtime monitor of field programmable gate array (FPGA) or complex programmable logic device (CPLD) code written in VHDL. Each spider is associated with specific logic statements expressing conditions in the code being monitored. Each spider also contains mechanisms for mitigating the effects of an exploit, either malicious, due to an error in design, or due to a hardware fault. The spider for this example was hand compiled from logic statements into VHDL code that is combined with the traffic light code before vendor tools compile everything into an internal representation. Spiders can be written in any language provided there is a translator into a language vendor supplied tools support. Eventually, spiders will be automatically compiled from logic statements and mitigation code to produce either VHDL code or ReWire code. ReWire has its own compiler that produces either VHDL or Verilog code, which would then subsequently be included in the application.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 23, 2022
- Accession Number
- AD1172840
Entities
People
- Christopher Belmonte
- Gerard Allwein
Organizations
- United States Naval Research Laboratory