Continuous-Time Pipeline Level-Crossing Analog-to-Digital Converter and Continuous-Time Software-Reconfigurable Radio Architecture
Abstract
The field of signal processing consists of several areas, each of which has its own set of advantages and limitations. A new subfield of signal processing called continuous-time systems has some unique signal-processing characteristics. To better understand continuous-time systems, a review of analog signal processing and conventional digital signal processing (DSP) is presented first. Continuous-time systems behave similar to analog signal-processing systems with the benefits of discrete amplitude levels from DSP. Continuous-time systems also have the benefits of analog signal processing (power is proportional to slope of the input signal) without the limitations of conventional DSP: frequency aliasing, quantization error, and control system lag. Continuous-time systems with greater than 100 dB signal-to-noise ratio have been demonstrated; such systems are more energy efficient than DSP. In this technical report, a patent-pending continuous-time pipeline analog-to-digital converter (CT-ADC) is presented. The CT-ADC overcomes several design limitations present in conventional clocked ADCs. The CT-ADC topology can also be used in a conventional clocked pipeline ADC to reduce the complexity of error correction. A patent-pending continuous-time software-reconfigurable radio (CT-SRR) based on the CT-ADC is also described. The CT-SRR architecture overcomes dynamic range and intermodulation distortion problems present in conventional software-reconfigurable radios.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 01, 2022
- Accession Number
- AD1175477
Entities
People
- Patrick Jungwirth
- W. M. Crowe
Organizations
- United States Army Research Laboratory