Implementation and Characterization of AHR on a Xilinx FPGA
Abstract
The Adaptive-Hybrid Redundancy (AHR) architecture was modified and tested in hardware using Commercial-Off-The-Shelf (COTS) Field-Programmable Gate Arrays (FPGAs). The AHR architecture mitigates the effects that the Single Event Upset (SEU) and Single Event Transient (SET) radiation effects have on processors and was tested on a Microprocessor without Interlocked Pipeline Stages (MIPS) architecture. The AHR MIPS architecture was implemented on two Xilinx FPGAs using a serial based communication network. The runtime performance of AHR MIPS was measured and compared against the performance of TMR and TSR MIPS. AHR MIPS demonstrated flexible runtime performance that was nearly as fast as TMR MIPS, never as slow as TSR MIPS, and demonstrated performance in between those extremes. Hardware testing and verification of AHR MIPS showed that the AHR mitigation strategy presents a large performance trade space, where a user can adjust both the runtime processor performance and radiation tolerance to fit the constraints of a space mission.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 24, 2022
- Accession Number
- AD1175768
Entities
People
- Andrew J Dittrich
Organizations
- Air Force Institute of Technology