Modeling Graph Neural Networks for Gate Level Arrival Time Prediction of Long Tailed Datasets
Abstract
Iterative re-calibration of the design parameters to meet timing closure is a critical and computationally costly component of the overall integrated circuit (IC) design flow. By predicting timing profiles at the initial stages of the design flow, early modifications to the circuit reduce overall design time .In this work, a graph-based deep regression model is utilized for the prediction of the gate-level arrival time of the timing paths of a circuit. Three scenarios for the post-routing prediction of timing path arrival time are considered: prediction after floorplanning, prediction after placement, and prediction after clock tree synthesis (CTS). A commercial static timing analysis tool is used to determine the mean absolute percentage error (MAPE) and mean absolute error (MAE) for each scenario. Results obtained across all models trained on the complete dataset indicate that the proposed methodology outperforms the baseline errors produced by commercial physical design tools, with an average improvement of 61.58% in the MAPE score when predicting the post-routing arrival time after floor planning and a 13.53% improvement when predicting the post-routing arrival time after placement. Given the long-tailed nature of the data, further prediction scenarios are analyzed, where the complete dataset is subdivided based on both circuit size (small, medium, and large) and timing path size (timing path logical depths of less than 5 and timing path logical depths greater than or equal to 5). Models trained for small and medium datasets result in an average MAPE of 2.61% and 4.03%, respectively, while the average MAPE of the complete dataset is approximately 24.47%.Similarly, models trained on datasets with timing paths of logical depths < 5 and logical depths >= 5 result in an average MAPE of 24.01% and 15.62%, respectively.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 20, 2023
- Accession Number
- AD1198355
Entities
People
- Ioannis Savidis
- Pratik Shrestha
- Saran Phatharodom
Organizations
- Drexel University