Physically Secure Hardware Redaction and Logic Locking with Hybrid Logic Systems

Abstract

While hardware obfuscation techniques like logic locking and hardware redaction can secure chips against algorithmic attacks, security against physical attacks requires the use of emerging technologies with large error rates. Hybrid logic systems have therefore been proposed in which polymorphic islands with physical security provide algorithmic security within a large CMOS system. In this work, we demonstrate that a well-chosen encryption of small, physically secure islands embedded in a physically insecure technology is sufficient to secure the entire chip against algorithmic and physical attacks.

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Document Details

Document Type
Technical Report
Publication Date
Mar 20, 2023
Accession Number
AD1198470

Entities

People

  • Alexander J. Edwards
  • Alexander N. Chin
  • Jared D. Arzate
  • Joseph S. Friedman
  • Naimul Hassan
  • Yiorgos Makris

Organizations

  • University of Texas at Dallas

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Automation
  • Circuits
  • Complementary Metal-Oxide Semiconductors
  • Cryptography
  • Dictionaries
  • Domain Walls
  • Emerging Technology
  • Engineering
  • Fabrication
  • Fault Tolerance
  • Integrated Circuits
  • Logic
  • Logic Gates
  • Magnetic Domains
  • Physical Security
  • Security
  • Semiconductors
  • Visibility

Fields of Study

  • Computer science
  • Mathematics

Readers

  • Computational Linguistics
  • Cybersecurity.
  • Integrated Circuit Design and Technology.