Fully-Autonomous System-on-Chip (SoC) Synthesis Using Customizable Cell-Based Synthesizable Analog Circuits
Abstract
This project is a collaboration between the Universities of Michigan (lead) and Virginia, and ARM plc, Inc. Our approach leverages a differentiating technology to automatically synthesize "correct-by-construction" Verilog descriptions for both analog and digital circuits and enable a portable, single pass implementation flow. The SoC synthesis tool realizes analog circuits, including PLLs, power management, ADCs, and sensor interfaces by recasting them as structures composed largely of digital components while maintaining analog performance. They are then expressed as synthesizable Verilog blocks composed of digital standard cells augmented with a few auxiliary cells generated with an automatic cell generation tool. By expanding the IPXACT format and the Socrates tool from ARM, we then enable composition of vast numbers of digital and analog components into a single correct-by-construction design. Latency insensitive interfaces between blocks enable single pass timing closure.
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 01, 2023
- Accession Number
- AD1208692
Entities
People
- David D. Wentzloff
Organizations
- University of Michigan