Basic Distributed Logic for Spiders
Abstract
This is a report on using Distributed Logic for spiders. A spider is a real time monitor for FPGA applications. Each spider is specific to an application. The mental picture is that the body of a spider sits over an application and its legs stick down into the application. Signals travel up and down the legs. The signals to the spider are recognition signals and report on conditions in the application. Signals from the spider are mitigation signals and direct the application to perform behavior outside of its normal operation. The mitigation may require specialized code in the application to respond properly to the mitigation. A spider is written in any language for FPGA applications such as VHDL or Verilog. We prefer to use ReWire, which is a functional language that compiles to VHDL or Verilog. A spider in compiled form is then included along with the application and the lot is further processed by vendor tools to eventually become a file loaded onto an FPGA. This file is the FPGA application + spider and defines that application + spider. An FPGA can bethought of a clean slate of transistors what only receive their instructions on how to act by virtue of this file
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 17, 2023
- Accession Number
- AD1208906
Entities
People
- Christopher Belmonte
- Gerard Allwein
Organizations
- United States Naval Research Laboratory