An Automatic Intellectual Property (IP) Generator for Customizable Field Programmable Gate Array (FPGA) Architectures

Abstract

This project describes the development of an automatic IP generator for customizable FPGA architectures, as key element to kick-start a viable open-source System-On-Chips (SoC) ecosystem as defined in DARPA ERI POSH program, Technical Area 2 (TA-2). Such tool can significantly reduce the development and research time required to embed custom FPGAs into SoCs, especially for DoD applications, such as next-generation unmanned aerial vehicles and advanced wireless/ Software Defined Radio (SDR) designs.

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 2023
Accession Number
AD1212056

Entities

People

  • Pierre-Emmanuel Gaillardon

Organizations

  • University of Utah

Tags

Communities of Interest

  • Advanced Electronics
  • Cyber
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Air Force
  • Air Force Research Laboratories
  • Application-Specific Integrated Circuits
  • Circuits
  • Computer Programming
  • Computer Programs
  • Computer-Aided Design
  • Debugging
  • Fabrication
  • Field Programmable Gate Arrays
  • Generators
  • Governments
  • Integrated Circuits
  • Intellectual Property
  • Operating Systems
  • Semiconductor Manufacturing
  • Semiconductors
  • Shell Scripts
  • Unmanned Vehicles
  • Very Large Scale Integration
  • Waveforms
  • Xml

Fields of Study

  • Computer science

Readers

  • Aerospace Test and Evaluation
  • Cybersecurity.
  • Integrated Circuit Design and Technology.

Technology Areas

  • Autonomy