Resilient Analog Instance Language (RAIL) Enabled Open-Source Mixed Signal Circuits
Abstract
The objective of this research is to develop RAIL, an agile analog and mixed-signal (AMS) design methodology and its demonstration on the implementation of four open-source mixed-signal integrated circuit intellectual properties (IPs): analog to digital converters (ADCs), delay-locked loops (DLLs), low dropout voltage regulators (LDOs), and LPDDR4X memory interface circuits. These four types of mixed-signal circuits are crucial building blocks for complex systems-on-chip (SoC) development, thus are essential for achieving the complete open-source SoC implementation. However, unlike digital RTL design that can be open sourced easily in the form of register-transfer level (RTL) description using the industry-standard Verilog hardware description language and realized by using the industry automated place and route design flow, these analog and mixed signal designs are designed manually based on analog designers' experience using schematic capture tools and simulators, then laid out manually with layout editor tools. Simulation of these blocks is performed using SPICE-like circuit simulators and is not compatible and hard to be integrated with Verilog simulators. The realization and even the design of mixed-signal blocks are process dependent, rely on proprietary physical design kits (PDKs) from the fabrication foundries, which further hinder the process of opensource mixed-signa SoC innovation. The project is built on top of recently digitalized analog design architectures tailed for deep submicron digital-centric fabrication process. RAIL defines a basic set of analog and mixed-signal primitives including delay-sensitive logic gates, switches, passives, differential pairs, and et al. State-of-the-art SAR-ADC,MDLL, LDO and LPDDR4x architectures and circuit implementations are all mapped with this set of primitives and standard digital cells.
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 01, 2023
- Accession Number
- AD1214541
Entities
People
- C. R. Shi
Organizations
- University of Washington