A Study of Fault Diagnosis of Sequential Logic Networks.

Abstract

The research conducted on this project was concerned with the problem of test pattern generation for sequential logic circuits. More specifically, an algorithm was sought for generating test patterns for detecting single stuck-at faults in synchronous sequential circuits containing clocked flip-flop memory elements. In addition to the principal problem stated above, the related problems of test pattern generation for combinational iterative logic arrays and of test pattern generation for multiple faults in combinational logic circuits were also studied. A summary of the results obtained and the conclusions reached on the above problems is given. Suggestions for follow-on studies are discussed. Reprints of all papers published on the project are included in an appendix.

Document Details

Document Type
Technical Report
Publication Date
Oct 31, 1974
Accession Number
ADA001831

Entities

People

  • B. D. Carroll

Organizations

  • Auburn University

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Circuits
  • Demographic Cohorts
  • Electrical Circuits
  • Electrical Equipment
  • Electronic Circuits
  • Logic
  • Logic Gates
  • Networks

Readers

  • Fault Tolerant Diagnosis of Black and White Balloon Isolation Tests Using ¥.
  • Integrated Circuit Design and Technology.
  • Technical Research and Report Writing.