EMP Hardened CMOS Circuits.
Abstract
A survey and testing program has shown that standard CMOS circuits will not survive EMP induced surges of more than 200 volts from a 50-ohm source. However, an analysis of the failure mechanism showed that Bulk CMOS integrated circuits could be readily modified to survive EMP surges of up to 5,000 volts from a 50-ohm source. This new monolithic protection circuit is compatible with existing CMOS processing, and represents an extension of existing networks for static discharge protection. Assuming equal production quantities, the cost of EMP protected circuits in ceramic packages would be only 7% higher than for standard units. A 2 to 1 speed degradation is expected, although this effect could be reduced by increasing output transistor drive capability.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 1973
- Accession Number
- ADA004034
Entities
People
- Daniel Hampel
- Roger G. Stewart