Fault Detection through Parallel Processing in Boolean Algebra.

Abstract

This presentation is an overview of the research in progress on fault detection methods for circuits, both combinational circuits and sequential circuits. A summary of some of the existing techniques for minimal test set generation is followed by an introduction to the concept and theory of a minimal test sequence as a new approach for fault detection in combinational circuits. A detailed explanation of Triadic Graph Theory is followed by a summary of the existing techniques for parallel processing in Boolean Algebra. The main contribution of this paper is the extension of the applications of the Boolean Analyzer to the generation of: (1) Boolean Differences; (2) 'stuck-at' fault tests for a circuit (similar to those generated by Roth's D-Algorithm); and (3) the Test Sequence(s) of a circuit.

Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1975
Accession Number
ADA007552

Entities

People

  • Donnamaie E. White

Organizations

  • University of California, Los Angeles

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Analyzers
  • Boolean Algebra
  • Demographic Cohorts
  • Detection
  • Graph Theory
  • Mathematics
  • Parallel Computing
  • Parallel Processing
  • Sequences
  • Test Sets

Fields of Study

  • Engineering

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Computational Linguistics