Radiation-Hardened CMOS/SOS Standard Cell Circuits.
Abstract
The basic design procedure and the basic topology for a family of CMOS/SOS radiation-hardened standard cells were defined. The basic design procedure consisted of two principal steps. One involved the layout of the cells. To minimize the effect of radiation when back-biased, all substrates of stacked devices were connected to each other and to supply or ground. In the case of P-type stacked devices, both ends of the channel substrates were connected to V sub DD. The second step involved extensive detail design and simulation of the various circuit types to determine the device sizes. The radiation-induced upset levels of various circuit alternatives for the complex cells were analyzed. From this analysis came a set of guidelines for circuit design in terms of circuit complexity, use of transmission gates, etc. The initial design or layout for all of the adder cells was implemented. Several cells, representing various cell groups, were examined and analyzed in considerable detail to permit verification of selected device sizes. The logic configuration of the test chip was defined.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 1975
- Accession Number
- ADA013016
Entities
People
- A. Feller
- R. L. Pryor