High Data Rate Magnetic Memory Devices.
Abstract
This report presents the results of a system and cost study made to determine the feasibility of developing a bubble domain BORAM chip using existing device components. Due to the short access time requirements the major-minor loop chip organization cannot be used and due to the lack of a decoder of the necessary type with adequate margins, an alternative chip scheme is proposed in which parallel access to storage loops is achieved via separate transfer switches. The feasibility of realizing such a chip is examined from the viewpoint and preliminary designs are proposed. Estimates of the system costs and optimum chip capacity are made based upon a simple yield model for bubble devices. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 01, 1975
- Accession Number
- ADA013510
Entities
People
- L. R. Tocci
- O. D. Bohning
- P. K. George