Radiation-Hardened CMOS/SOS Standard Cell Circuits.
Abstract
The design, layout, simulation and characterization of all of the cells in the CMOS/SOS radiation hardened standard cell family were completed, with but one exception. Data sheets were generated providing design information for each of the cells. Among the information included in the data sheets are stage delay and transition times for preradiation and for the worst-case end of total dose 10 to the 6th power rads; input and output capacitances; logic and circuit configurations; truth table; and other design data. Two LSI arrays are being designed to provide experimental evaluation, characterization, and validation of the radiation-hardened CMOS/SOS circuits. One of these arrays, a test chip with more than 30 tests on it, permits measurements to be taken directly on each of the cells. This provides for determining the effect of total dose and dose rate on the leakage, performance, and reliability of each of the cells. An analysis was completed to determine specifically what changes must be made in the present adder in order to generate the radiation-hardened version. Essentially, this involved the replacement of the radiation-hardened cells for the presently used cells, the elimination of the transmission gate through the arrays, and the elimination of all gates with four or more inputs.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 1975
- Accession Number
- ADA017021
Entities
People
- A. Feller
- R. L. Pryor