High Performance Emulation.
Abstract
The Stanford EMMY is examined as an emulation engine. Using the 360 emulator and the DELtran interpreter as examples, the performance of the current EMMY architecture is examined as a high performance emulation vehicle. The problems of using a sequential, vertically organized processor for high speed emulation are developed and discussed. A flexible control structure for high speed emulation studies is derived from an existing high performance processor. This structure issues a stream of microinstructions to a central command bus, allowing user-defined execution resources to execute them in overlapped fashion. These execution resources may be added or deleted with little or no processor rewiring. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 01, 1975
- Accession Number
- ADA020665
Entities
People
- Walter A. Wallach Jr.
Organizations
- Stanford University