Reduction of Depth of Boolean Networks with a Fan-In Constraint.

Abstract

In this paper a family of techniques for the design of combinational networks whose objective is the reduction of the number of levels, subject to a constraint on the fan-in of the logic gates are presented.

Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1975
Accession Number
ADA021662

Entities

People

  • A. B. Barak
  • D. E. Muller
  • Franco P. Preparata

Organizations

  • University of Illinois Urbana–Champaign

Tags

DTIC Thesaurus Topics

  • Circuits
  • Electrical Circuits
  • Electrical Equipment
  • Electronic Circuits
  • Logic
  • Logic Gates
  • Networks

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Business Analytics