Radiation-Hardened CMOS/SOS Standard Cell Circuits.
Abstract
Two versions of the radiation-hardened CMOS/SOS standard cell test chip were fabricated during this quarter. One set of test chips was processed using the CMOS/SOS process with the standard oxide. The objective of these chips is to provide verification of the design and layout of the family of standard cell circuits, all of which are used in the 8-bit multiplexed adder chip. The second set of test chips, using the same set of masks, was fabricated with the radiation-hard process using the clean, dry oxide. Twenty of the test chips were received and tested. All of the cell types were checked and operated normally. The design and layout of the 8-bit multiplexed adder chip were completed and triple-checked. The 80X artwork was generated. The adder artwork was not submitted to the mask fabrication cycle pending the results of the measurements on the standard oxide test chips. Now that these tests have been made and the correct functionality of all of the cell types validated, the adder artwork can now proceed through the mask and fabrication cycle.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1975
- Accession Number
- ADA021738
Entities
People
- A. Feller
- R. L. Pryor