Automated Multiple Fault Test Generation for Combinational Networks.

Abstract

This report deals with multiple fault detection in combinational logic networks; the faults considered are those which may be represented by one or more lines stuck at logic value 0 or 1. Some new theorems and rules are presented which aid in the identification of masking faults, and an algorithm is developed which produces multiple fault detection test sets for single-output combinational logic networks. The algorithm uses a path sensitizing technique to generate tests for members of a set of prime faults; any network fault can be represented by a combination of faults from the prime fault set, and a test which detects all combinations of prime faults will detect any single or multiple fault in the network. A modified version of the algorithm is implemented in the FORTRAN computer programming language; the automated version produces test sets which are optimal or near-optimal and usually complete. In the test generation process, certain redundancies are also detected.

Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1976
Accession Number
ADA023174

Entities

People

  • Robert A. Hendrix

Organizations

  • Air Force Institute of Technology

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Computer Programming
  • Computers
  • Demographic Cohorts
  • Detection
  • Identification
  • Language
  • Logic
  • Logic Gates
  • Networks
  • Programming Languages
  • Redundancy
  • Test Sets

Fields of Study

  • Computer science

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Fault Tolerant Diagnosis of Black and White Balloon Isolation Tests Using ¥.