Maximal Clocking Rates for Pipelined Digital Systems.
Abstract
Constraints are derived for controlling the clock inputs to the storage registers of a synchronously controlled pipelined digital system. Limits on the clock width, clock period, and clock skew between segments of the pipeline are described in terms of the propagation delay times of the logic elements of the network. Separate constraints are developed for pipelines using three different types of register elements: Earle latches, D-latches, and edge-triggered flip-flops. A 2-segment, 16-bit pipelined adder is used to test and the timing constraints, including an analysis of the propagation delays of the logic elements in the sample network. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1975
- Accession Number
- ADA025611
Entities
People
- Bradly Kevin Fawcett
Organizations
- University of Illinois Urbana–Champaign