A Virtual Memory System for the PDP-10 KA10 Processor.

Abstract

This report describes the development of the Large Space Virtual Memory System for operation with a Digital Equipment Corporation PDP-10 Computer system. The virtual memory system modifies the KA10 instruction set and addressing mechanisms to provide a virtual memory address space of 2 to the 36th power 36-bit words. Each address consists of a 9 bit segment number and a 27 bit within segment address. The VM control programs are based on a new page replacement algorithm, the Page Fault Frequency (PFF) Replacement Algorithm, called the Shared PFF (SPFF). (Author)

Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1976
Accession Number
ADA028987

Entities

People

  • L. P. Mcnamee

Organizations

  • University of California, Los Angeles

Tags

DTIC Thesaurus Topics

  • Addressing
  • Algorithms
  • Computers
  • Corporations
  • Frequency
  • Instruction Set Architecture
  • Instructions

Readers

  • Computer Science.
  • Electrical Engineering
  • Team-Based Human-Centered Cognitive Task Decision Making and Information Performance.

Technology Areas

  • Space