A Charge-Coupled Device (CCD) Memory for Navy C3 Systems

Abstract

A prototype memory system using 16 thousand-bit charge-coupled devices and a microprocessor controller has been designed and tested. Features include a modular, expandable architecture, error detection and correction, NTDS input and output, and SHP packaging.

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Document Details

Document Type
Technical Report
Publication Date
Jul 30, 1976
Accession Number
ADA030902

Entities

People

  • J. J. Symanski

Organizations

  • Navy Electronics Laboratory

Tags

Communities of Interest

  • Advanced Electronics
  • Ground and Sea Platforms
  • Materials and Manufacturing Processes
  • Space

DTIC Thesaurus Topics

  • Charge Coupled Devices
  • Clocks
  • Computer Programming
  • Computers
  • Computing System Architectures
  • Data Storage Systems
  • Debugging
  • Digital Images
  • Electronics
  • Electronics Laboratories
  • Instruction Set Architecture
  • Instructions
  • Mass Storage
  • Metal Nitride Oxide Semiconductors
  • Microprocessors
  • Semiconductors
  • Software Development

Fields of Study

  • Physics

Readers

  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.
  • Integrated Circuit Design and Technology.

Technology Areas

  • Fully Networked C3
  • Fully Networked C3 - Command and Control