A Processor Utilization Model for a Multiprocessor Computer System.

Abstract

In this paper a processor utilization model for a simplified multi-processor computer system is developed using a G/M/s/N queueing system model. The mathematical model is based on the busy period analysis, and two utilization measures are derived: (1) Processor utilization (the fraction of processor occupation time during a busy cycle), and (2) System utilization (the fraction of actual utilization time for all processors). Experimentation with the computational model reveals the sensitivity of the model to variability in the arrival process. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1976
Accession Number
ADA032660

Entities

People

  • Richard E. Nance
  • U. Narayan Bhat

Organizations

  • Southern Methodist University

Tags

DTIC Thesaurus Topics

  • Bibliographies
  • Computer Programming
  • Computers
  • Engineering
  • Industrial Engineering
  • Markov Chains
  • Mathematical Models
  • Models
  • Operations Research
  • Parallel Computing
  • Parallel Processing
  • Parallel Processors
  • Probability
  • Probability Distributions
  • Random Variables
  • Scheduling (Production)
  • Sensitivity

Fields of Study

  • Engineering

Readers

  • Life Cycle Cost Analysis
  • Mathematical Modeling and Probability Theory.
  • Parallel and Distributed Computing.