Associative Processor I/O Design and Specification.

Abstract

Detailed input/output (I/O) specifications were compiled for the three interface channels that currently exist in the STARAN associative processing computer at RADC: (1) buffered I/O (BIO), (2) direct memory access (DMA), and (3) external function (EXF). The availability and location of port connections for these channels are included within the I/O specifications. A comprehensive philosophy was developed that provides an interface between various external devices and the parallel input/output PIO unit. The recommended PIO expansion method uses a daisy-chain approach, where each external device is constrained to repeat all the signal of the PIO channel. The expansion method contains a control channel and four 256-bit-wide data ports. These data ports connect external devices to the PIO unit. The associative arrays also connect to the PIO unit through four existing ports. Since the associative array ports contain intermediate buffer registers, the recommended expansion data ports are not buffered. To minimize the number of cable wires and signal repeaters, the PIO expansion approach uses bi-directional lines and time-multiplexed data transmission. In this way, 32 lines are used to transmit a 256-bit-data word in either direction. A detailed logic design of the recommended PIO expansion philosophy was completed; three new PC boards were designed as part of this effort. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1976
Accession Number
ADA034658

Entities

People

  • Michael J. Kroeger

Organizations

  • Goodyear Aerospace

Tags

Communities of Interest

  • Space

DTIC Thesaurus Topics

  • Associative Processing
  • Circuit Boards
  • Computers
  • Content Addressable Memory
  • Control
  • Data Transmission
  • Manipulators
  • Network Topology
  • Parallel Computing
  • Parallel Processing
  • Printed Circuits
  • Repeaters
  • Security
  • Specifications
  • Standards
  • Test And Evaluation
  • Time

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  • Computer Engineering
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