An Architectural Study of Signal Processing Systems and Switched Networks. Volume 3. Appendix L. Computer Listings and Runs.
Abstract
Contents: Program listing of the general simulation model for a bus architecture (FMODEL); Program listing of the Report formater (FREPORT); Listing of the Signal Processing Module library (SPMODULE); Listing of the Switching System Module library (SWMODULE); Listing of Signal Processing Simulation Runs; and Listings of Switching System Simulation Run.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 15, 1977
- Accession Number
- ADA040284