Advanced Signal Processing Software Verification and Validation.
Abstract
The Computer Family Architecture Project has as its stated mission the selection of a commercially available computer architecture that would provide the basis for a family of military computers in the 1980's. In order to make a valid selection, the parent project gave birth to sibling efforts involving the design, development, verification, and validation of (1) an Architecture Research Facility (ARF) and (2) a set of candidate architecture benchmark test programs. A computer architecture can be described on the ARF using the instruction Set Processor Language (ISPL) for which the ARF has a compiler. Using the simulation capabilities of the ARF, the benchmark test programs were to indicate the performance characteristics of the candidate computer architectures in a quantifiable manner. The CFA selection committe could then select the best architecture based on quantitatively justifiable figures of merit derived from evaluating benchmark performance on the ARF simulator corresponding to each of the particular architecture descriptions. The ARF approach provided a controlled environment in which to effectively execute a comparative study of computer architectures at the instruction set level.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1976
- Accession Number
- ADA040956