Design Considerations and Trade-Offs in MOS/LSI.

Abstract

In order to be cost-effective, digital circuits implemented in MOS large scale integration (LSI) are designed with close regard to optimality. Three criteria - power dissipation, chip area (cost), and speed - are balanced to produce a final circuit. Current practices involve a significant amount of simulation to determine the most satisfactory trade-offs. This project is concerned with the prediction of optimal values of certain design parameters for a given function of the above three criteria. This paper first develops a simplified model for MOS/LSI circuits. Using this model, equations are derived for circuit speed, power dissipation, and area. These equations are expressed as functions of the channel dimensions of the MOS transistors and of the degree of pipelining of the circuit. These three equations, and their pairwise products, are then optimized. The relationships between the equations and the parameters are examined. The effects and trade-offs of particular design choices are described. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Apr 01, 1977
Accession Number
ADA041687

Entities

People

  • Alan Dale Gant

Organizations

  • University of Illinois Urbana–Champaign

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Air Force
  • Circuits
  • Digital Circuits
  • Dissipation
  • Electronics
  • Equations
  • Integrated Circuits
  • Inverters
  • Large Scale Integration
  • Logic Gates
  • Metal Oxide Semiconductors
  • New York
  • Power
  • Power Electronics
  • Semiconductors
  • Transistors
  • United States

Fields of Study

  • Engineering

Readers

  • Fluid Dynamics.
  • Integrated Circuit Design and Technology.
  • Operations Research