LSI Electronically Programmable Arrays: Configurable Polynomial Arrays.
Abstract
The basic objective was the realization of parallel array architectures utilizing LSI distributed logic/memory circuit with the capability of being programmed or trained to perform a variety of signal processing functions. A 32 bit floating point CMOS/SOS cell was developed and a circuit configuration of 8 of these cells realized the desired element. The element computes a general parametric equation of two inputs and one output. The thruput computation time ranges from 10 sec to 3.5 sec depending on whether all or part of the above expression is desired in computation. Trade-off studies were carried out with respect to alternate realizations. Bit precision vs speed. Bit precision vs. application and complexity vs cost. The element was realized and demonstrated with respect to computational capabilities. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 1977
- Accession Number
- ADA042256
Entities
People
- D. Cleveland
- D. Hampel
- K. Augustyn
- K. Prost
- R. L. Barron