An Algorithm for Minimizing Programmable Logic Array Realizations.

Abstract

Due to the increasing use PLAs (Programmable Logic Arrays) in logic design, and efficient algorithm which performs multiple-output AND-OR logic minimization is desired. Quine-McCluskey (QM) logic minimization has been known for some time. A new AND-OR minimization algorithm for logic problems with up to 16 inputs and 8 outputs (standard limitations of PLAs available at present) is needed. The algorithm should be particularly effective for problems which require no more than 40 to 50 product terms in an optimum realization. In this report, such an algorithm is formulated which strives to achieve an AND-OR realization with the smallest number of AND gates.

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Document Details

Document Type
Technical Report
Publication Date
Apr 01, 1977
Accession Number
ADA043361

Entities

People

  • Alphonso Gar-yau Soong

Organizations

  • University of Illinois Urbana–Champaign

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Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Computer Engineering
  • Operations Research