Fault Diagnosis of Semiconductor Random Access Memories.
Abstract
This report deals with the problems of testing semiconductor random access memories and of locating faults on a memory board. Memory test procedures can be divided into three classes, functional testing, pattern sensitivity testing and DC parametric testing. Existing test procedures for testing semiconductor memories are either limited in their fault coverage or require a prohibitive amount of time. A new functional test procedure based on a fault model that takes into account a large variety of faults encountered with semiconductor memories is presented. The fault model is not based on the 'gate' level as in classical fault diagnosis but is formulated on a higher level in terms of functional blocks, like the decoder and the memory cell array. The proposed functional test procedure takes 0(n x log sub 2) units of time where n is the number of words in memory. This gives a dramatic improvement in the testing time required over well-known test procedures line 'galpat' and 'Walking Ones' which take 0(n squared) units of time. Algorithms for the functional test procedure are given. The problem of locating faults on a memory board to memory chips, decoder logic, data registers, and bussing structure is discussed. A test scheme for this problem is given. Finally various test procedures presented in the thesis are evaluated for fault coverage, time requirement and east of implementation.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 1977
- Accession Number
- ADA044281
Entities
People
- Satish Mukund Thatte
Organizations
- University of Illinois Urbana–Champaign