High-Reliability, Low-Cost Integrated Circuits.

Abstract

Wafer fabrication is proceeding as scheduled. The technology development for platimum sputter etching using gold as the etch mask has progressed sufficiently to allow conversion of the COS/MOS circuits to sputter etching. Reliability data to date obtained on CA741 devices shows a 0.0044% per 1000 hours failure rate at 120 C at the 60-percent confidence level. Copper migration in epoxy packages at 125 C has not been observed as a failure mode. Salt atmosphere resistance tests to date have produced excellent results. All required life-test sockets for Phase II and some of the sockets for Phase III of the program have been ordered.

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Document Details

Document Type
Technical Report
Publication Date
Aug 03, 1977
Accession Number
ADA045089

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Aluminum
  • Ceramic Materials
  • Contracts
  • Electronics
  • Electronics Laboratories
  • Engineering
  • Failure Mode And Effect Analysis
  • Heat Of Activation
  • High Reliability
  • Integrated Circuits
  • Jet Propulsion
  • Life Tests
  • Materials
  • Nand Gates
  • Production
  • Quality Control
  • Semiconductors

Readers

  • Integrated Circuit Design and Technology.
  • Software Engineering
  • Thin Film Deposition Science.