A Structure Memory for Data Flow Computers
Abstract
A data flow computer is one which achieves enormous concurrency of instruction execution through a machine architecture that acts directly on a data dependency graph of the program. To handle arrays and data structures effectively a data flow computer must have access to a memory system which can handle large numbers of concurrent transactions. This thesis presents a design for such a memory. A cache mechanism is presented for improving the performance of the system, and a mechanism is given for using sequential-access devices such as shift registers as the memory medium. The memory system design uses the packet communication concept, in which the components of the system communicate only through the transmission of fixed size packets of data.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 1977
- Accession Number
- ADA047026
Entities
People
- William B. Ackerman
Organizations
- Massachusetts Institute of Technology