A Low-Power Digital Timer with Potentiometer Setting Mechanism.
Abstract
A digital electronic timer is described that uses the position of a potentiometer for time selection. Upon activation of a power supply, a counter in the timer is preset to the binary equivalent of the potentiometer setting and then proceeds to time out by counting from the preset state to overflow. The counting rate is determined by the frequency of a crystal controlled oscillator. During the time interval up to and including the preset cycle, the current drain of the circuit is 800 microamp. at 5.5 V. After completion of the preset operation, the current consumption drops to 20 microamp. at the reduced voltage of 3.6 V. This low operating power makes it possible to use this circuitry in a fuze with a fluidic power supply wherein a charged capacitor could bridge a temporary power loss during projectile flight through apogee. Although the system is described with a potentiometer as the input device, the electronic part is not so limited. This preset scheme can be used whenever the digital output from the counter can be converted into a single-valued time-varying function commensurate with a constant or quasi-constant input quantity, which is a function of the desired time delay.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 1977
- Accession Number
- ADA047799
Entities
People
- Friedrich W. Flad
Organizations
- Harry Diamond Laboratories